STEEPER was an ambitious EC project dealing with some of the most promising emerging energy efficient device architecture: the Tunnel FET exploiting the band-to-band quantum mechanical tunnelling. The project had clear objectives in terms of development of advanced technology platforms for Tunnel FETs, with CMOS compatibility and by using most appropriate additive technology boosters. Moreover, the project targeted to innovate at the level of new device architecture and develop advanced simulation tools and models enabling circuit design with this new device.

The main technological platforms demonstrated functional devices with some of the reported performances close to the best international reports and some of the integration methods (like the III-V on silicon) opening new paths for future performance evolutions. These evolutions are strongly supported by the model and simulations based predictions. The project also contributed with new concept ideas, like advances in the electrostatic doping investigations, Tunnel FET capacitorless memory and Electro-Hole Bilayer Tunnel FET.

Browse our detailed results pages on: